One type of flash cell is the 1T-UCP Flash cell (1T=one transistor, UCP=uniform channel programming). This cell has a relatively large module area overhead independent of the memory size. Therefore, module areas are relatively large for small memory sizes. This may be relevant, for example, in certain markets where the main volume is achieved with products that have flash memory sizes in the range from about 100 kB to a few 100 kB. An additional boundary condition for these markets may be achieving a high write/erase endurance (write/erase cycle stability).
A conventional embedded flash (eFlash) cell concept optimized for low memory densities is the so-called SST ESF-1 cell shown in FIG. 15.
The flash cell 1500 shown in FIG. 15 includes a source 1502 and a drain 1503, which are formed in a substrate 1501. An insulating layer 1505 is formed on a channel region 1504 formed in the substrate 1501 between the source 1502 and the drain 1503, and on the source 1502. The flash cell 1500 is based on a split-gate concept, wherein a first polysilicon gate 1506 (“Poly 1”) is formed within the insulating layer 1505, and a second polysilicon gate 1507 (“Poly 2”) is formed on the insulating layer 1505 and partially overlaps the first polysilicon gate 1506 with the two gates 1506, 1507 being electrically insulated from one another by the insulating layer 1505.
The flash cell 1500 has the following properties: i) relatively low endurance (10 k-100 k cycles) due to the field enhanced poly/poly erase mechanism used; ii) the split-gate concept requires high overlay accuracy in lithography processes; iii) the scalability of the cell is relatively limited due to the large source underdiffusion needed.